An example of a conventional OFDM demodulation circuit is disclosed in JP Patent Publication (Kokai) No. 11-145930 A (1999).
FIG. 9 shows an example of the frame format of a packet used in the conventional OFDM demodulation circuit.
At the head of the frame of a packet P, a preamble signal is attached that is used for carrier frequency error detection, symbol synchronization or other purposes. The preamble signal is formed by a repetition of two identical, known start symbols SS.
These two start symbols SS as the preamble signal are followed by the repetition of a guard interval GI and a data symbol DS in packet P.
The two start symbols SS as the preamble signal and the data symbols DS each have a length of interval Tw on the time axis. This length Tw is the same as the width of the window for IFFT (Inverse Fast Fourier Transform) and FFT (Fast Fourier Transform) that are used for modulating and demodulating an OFDM signal, which will be described later.
Guard interval GI is inserted before data symbol DS in order to eliminate the influence of delayed waves. The length of its interval on the time axis is Tw/4 in this example.
FIG. 10 shows a block diagram of a conventional OFDM modulation circuit.
In conventional OFDM modulation circuit 400, an input information signal is fed to a serial-parallel converter 401 and is converted into information signals for each sub-carrier.
Output signals (information signals for sub-carriers) from serial-parallel converter 401 are fed to code modulators 402 and are subjected to code modulation, such as QPSK (Quadri-Phase Shift Keying).
Output signals (code-modulated information signals for individual sub-carriers) from coded demodulators 402 are fed to an IFFT converter 403 and are IFFT-converted into digital modulated waves having time-axis waveforms.
Output signals (digital modulated waves) from IFFT converter 403 are fed to a guard interval insertion circuit 404, where a guard interval GI is attached to them.
Output signals (data symbols DS to which guard intervals GI are attached) from guard interval insertion circuit 404 are converted into serial data in a parallel-serial converter 405.
An output signal from serial-parallel converter 405 is fed to an input switching circuit 406 which outputs an OFDM modulated signal while switching between the output signal from parallel-serial converter 405 and a preamble signal read from memory circuit 407.
The output signal from input switching circuit 406, namely the OFDM modulated signal as shown in FIG. 9, is fed to a D/A converter 408 and is converted into an analog signal, which is then outputted as a modulation baseband signal.
FIG. 11 shows a block diagram of a conventional OFDM demodulation circuit.
In conventional OEDM demodulation circuit 500, an OFDM reception signal that is obtained by A/D converting a received signal (modulation baseband signal that has been received) is fed to a delay circuit 501, a multiplier 503, a squarer 513, and a delay circuit 551.
The OFDM received signal fed to delay circuit 501 is delayed by the aforementioned time Tw.
An output signal from delay circuit 501 is fed to a complex conjugate signal generating circuit 502.
A conjugate complex signal generated in complex conjugate signal generating circuit 502 is subjected to complex multiplication with the current received signal in multiplier 503, thereby calculating a crosscorrelation value between those signals. An output signal from multiplier 503 is fed to a moving average filter 504.
In moving average filter 504, the output of multiplier 503 is moving-averaged to perform averaging over time Tw. An output signal from moving average filter 504 is fed to squarer 505 and converted into an electric power signal. An output signal from squarer 505 is fed to a peak detector 521.
The OFDM received signal fed to squarer 513 is squared therein and is then fed to moving average filter 514 as an autocorrelation value.
In moving average filter 514, the output of squarer 513 is moving-averaged to perform averaging over time Tw. An output signal from moving average filter 514 is fed to squarer 515 and converted into an electric power signal. An output signal from squarer 515 is fed to a peak detector 521.
In peak detector 521, to which input signals are fed from moving average filters 504 and 514 via squarers 505 and 515, respectively, peak detection is performed using these input signals (electric power signals).
Peak detector 521 determines a peak based on the magnitude of a signal obtained by dividing the output signal from squarer 505 by the output signal from squarer 515, for example. Peak detector 521 then outputs a symbol timing signal that indicates the timing at which the peak is detected.
Specifically, the fact that the peak has been detected in peak detector 521 indicates that a packet of the OFDM received signal has been received. Thus, based on the symbol timing signal, a process is initiated for demodulating the received packet of the OFDM received signal.
Thus, it can be said that aforementioned delay circuit 501, complex conjugate signal generating circuit 502, multiplier 503, moving average filter 504, squarers 505 and 513, moving average filter 514, squarer 515 and peak detector 521 together constitute a symbol timing signal detector 530.
Using the symbol timing signal from peak detector 521 and the output signal from moving average filter 504, a carrier frequency error detector 541 detects a carrier frequency error.
Meanwhile, an FFT window control circuit 542 outputs a control signal for window timing control, in accordance with the symbol timing control signal from peak detector 521.
While the above-described signal processing is performed by symbol timing signal detector 530, carrier frequency error detector 541 and FFT window control circuit 542, the OFDM received signal is delayed by delay circuit 551 and is then outputted to a phase rotator 552.
Based on the input of the control signal from FFT window control circuit 542, phase rotator 552 rotates the phase of an output signal from delay circuit 551 in accordance with an output signal from carrier frequency error detector 541. The frequency offset of the OFDM received signal is thus compensated for before the signal is fed to a guard interval eliminating circuit 553.
Based on the symbol timing signal, guard interval eliminating circuit 553 removes guard interval GI from the output signal from phase rotator 552, namely the OFDM received signal in which the frequency offset has been compensated for.
In serial-parallel converter 554, the output signal from guard interval eliminating circuit 553, namely the OFDM signal from which the guard intervals GI have been removed, is serial-to-parallel converted, thereby turning the OFDM received signal back into code-modulated information signals for individual sub-carriers, which are then fed to an FFT converter 555.
FFT converter 555 fast Fourier-converts the signal supplied from serial-parallel converter 554, thereby demodulating the time-domain signal into a frequency-domain signal. The thus demodulated code-modulated information signal is fed to a parallel-serial converter 556.
The code-modulated information signals converted by parallel-serial converter 556 into serial data are then fed to an error correction demodulator 557. Error correction demodulator 557 performs error-correction demodulation and outputs a demodulated input information signal (received information data) as an output signal.
An error detector 558 receives the output signal from error correction demodulator 557, namely the demodulated input information signal, and carries out error detection for the received signal.
In the aforementioned conventional OFDM demodulating circuit 500, a correlation value between the OFDM received signal and the OFDM received signal delayed by time Tw is obtained. Time Tw is used as analysis time within which time moving average filters 504 and 514 perform averaging calculations.
FIG. 12 shows the temporal changes in the magnitude of the correlation value between the OFDM received signal and the OFDM received signal that has been delayed by time Tw as these signals are fed to moving average filters 504 and 514.
In the above-described conventional OFDM demodulation circuit 500, it is determined that a peak of the correlation value for initiating a demodulating process has been detected when the magnitude of the correlation value between the OFDM received signal and the OFDM received signal with delay time Tw, i.e., the magnitude of the correlation value between the output of moving average filter 514 and that of moving average filter 504, exceeds a predetermined threshold value Sth. Upon detection of the peak, a demodulation process is initiated.
FIG. 13 shows a flowchart of the processes performed in the conventional OFDM demodulation circuit 500.
OFDM demodulation circuit 500 performs various computing processes on the received signal (modulation baseband signal) for detecting the symbol timing signal in a received-signal awaiting state, such as delay computation, moving-average computation, and correlation computation (step S511). Upon detection of a peak of the magnitude of the correlation value between the OFDM received signal and the OFDM received signal with delay time Tw in the peak detecting process, namely, when it is detected that the correlation value has exceeded the threshold value Sth (step S512), the demodulation process is initiated (step S513).
By using the timing of this peak detection as the symbol timing, timing control for the FT window and the carrier-frequency error detection, for example, are conducted. Consequently, the OFDM received signal is FFT-processed by having its guard intervals GI removed, and the code-modulated information signal is subjected to error-correcting demodulation. The result of the error-correcting demodulation, i.e., the input information signal that has been demodulated, is subjected to the error detection process in an error detector 558 (step S 514).
If an error is detected by error detector 558 in the thus demodulated input information signal (step S 515), the information data that has been demodulated up to this point in time since the last peak detection is abandoned, and the routine returns to the received-signal awaiting state (step S 511).
If, on the other hand, no error is detected by error detector 558 in the demodulated input information signal, the information data that has been demodulated up to this point in time is outputted (step S 516).
As another example of the conventional OFDM demodulation circuit, an OFDM demodulation circuit of the unique-word delay detection scheme is disclosed in JP Patent Publication (Kokai) No. 10-164161 A (1998).
FIG. 14 shows a frame format of a packet used in the OFDM demodulation circuit of the unique-word delay detection scheme.
Each packet P is provided with a unique word UW at the start, followed by data D.
FIG. 15 shows a block diagram of a unique word delayed detection circuit applied to the OFDM demodulation circuit.
To the unique word delayed detection circuit (to be hereafter referred to as a UW delayed detection circuit) 600, a quasi-synchronous detection signal and a unique word input signal (to be hereafter referred to as a UW input signal) that repeats the same signal sequence as that of a unique word UW in the quasi-synchronous detection signal are inputted.
The quasi-synchronous detection signal is a signal obtained by subjecting a OFDM modulation signal into which a known unique word UW is inserted to quasi-synchronous detection. Specifically, the quasi-synchronous detection signal is obtained by synchronously detecting the OFDM modulated signal using a local oscillator signal independent from the OFDM modulated signal and with a frequency that is very close to the OFDM modulated signal, thereby demodulating the OFDM modulated signal into the baseband signal. Between the carrier wave of the OFDM modulated signal and the local oscillator signal, there generally exists a carrier frequency offset.
This quasi-synchronous detection signal, which is a double-row signal consisting of an in-phase signal and a orthogonal signal, is fed to a delay circuit 601 and delayed by N symbols (N being an arbitrary positive number).
An output signal from delay circuit 601 is fed to a complex conjugate signal generating circuit 602 and there subjected to complex conjugation.
In a multiplier 603, an output signal from complex conjugate signal generating circuit 602 is multiplied with the quasi-synchronous detection signal, i.e., the quasi-synchronous detection signal is subjected to N-symbol complex conjugate delay detection. The result of multiplication, namely an N-symbol complex conjugate delay detection signal of the quasi-synchronous signal, is fed to a correlator 620.
On the other hand, the UW input signal is N-symbol delayed in a delay circuit 611 while it is subjected to complex conjugation in a complex conjugate signal generating circuit 612.
In a multiplier 613, the output signals from these are multiplied to thereby subject the UW input signal to N-symbol complex conjugate delay detection. The result of multiplication, namely an N-symbol complex conjugate delay detection signal of the unique word UW, is fed to correlator 620.
In correlator 620, crosscorrelation is determined between the N-symbol complex conjugate delay detection signal of the quasi-coherent signal and the N-symbol complex conjugate delay detection signal of the unique word UW, over the entire length of all of the symbols of the unique word UW, as they are fed from multipliers 603 and 613.
FIG. 16 shows a block diagram of a conventional signal detection circuit to which the UW delay detection circuit 600 of FIG. 15 is applied.
In order to detect the position of the unique word UW and to extend the range of measurement while maintaining the frequency-offset measurement accuracy, signal detection circuit 700, which is based on UW delay detection circuit 600 of FIG. 15, has different operation modes. One is an initial acquisition mode (to be hereafter referred to as an IA mode), in which different UW delay detection circuits (“DDD(N)” and “DDD(N/2)” 720 and 730 with different numbers of delay symbols N and N/2 (where 0.5<N≦1), respectively, are provided. The other is a fine-tuning acquisition mode (to be hereafter referred to as an FA mode), in which a UW delay detection circuit (“DDD(4N)”) 740 where the number of delay symbols is 4N is provided.
In signal detection circuit 700, a first quasi-synchronous detection signal is fed to a sampler 701 as an input signal. Sampler 701 generates an output signal based on a sampling signal supplied from a sampling signal generator 702. The first quasi-synchronous detection signal is a signal obtained by subjecting an orthogonal modulated signal in which a known unique word UW is inserted into a data signal to quasi-synchronous detection.
An output signal from sampler 701 is supplied to a data buffer 710 where it is stored, while also being supplied to DDD(N) 720 and DDD(N/2) 730 with different numbers of delay symbols.
DDD(N) 720 finds crosscorrelation between an N-symbol complex conjugate delay detection signal of the quasi-synchronous detection signal and an N-symbol complex conjugate delay detection signal of the unique word UW, and then outputs a crosscorrelation signal to a unique word detector (to be hereafter referred to as a UW detector) 721 and a unique word phase operator (to be hereafter referred to as a UW phase operator) 722.
DDD(N/2) 730 finds crosscorrelation between an N/2 symbol complex conjugate delay detection signal of the quasi-synchronous detection signal and an N/2 symbol complex conjugate delay detection signal of the unique word UW, and then outputs a crosscorrelation signal to a UW phase operator 731.
UW detector 721 compares the electric power value of the crosscorrelation signal with a predetermined threshold Sth1′. If the power value of the crosscorrelation signal exceeds the threshold Sth1′, UW detector 721 outputs an IA-mode UW detection signal to data buffer 710.
Upon reception of the IA-mode UW detection signal, data buffer 710 outputs the output signal from sample 701 that has been stored, to a multiplier 711.
In UW phase operator 722, frequency offset information is obtained based on the crosscorrelation signals supplied from DDD(N) 720, and the information is fed to a phase combiner 723.
In UW phase operator 731, frequency offset information is obtained based on the crosscorrelation signals supplied from DDD(N/2) 730, and the information is fed to phase combiner 723.
In phase combiner 723, phases are combined based on the frequency offset information from UW phase operators 722 and 731, thereby generating frequency offset information concerning the carrier of the quasi-synchronous detection signal, namely IA-mode frequency offset information, which is then fed to a numerical control transmitter (“NCO”) 724.
NCO 724 generates a frequency correction signal based on the frequency offset information that has been phase-combined in phase combiner 723.
Multiplier 711 generates a quasi-synchronous detection signal by multiplying the quasi-synchronous detection signal from data buffer 710 and the frequency correction signal from NCO 724, the quasi-synchronous detection signal having its frequency offset reduced to substantially zero. The thus generated quasi-synchronous detection signal is fed to a matched filer 712 as a second quasi-synchronous detection signal. Matched filter 712 reduces the noise or adjacent channel interfering components included in the quasi-synchronous detection signal.
The quasi-synchronous detection signal outputted from matched filter 712 is delivered to a DDD(4N) 740 with 4 N delay symbols. DDD(4N) 740 produces a crosscorrelation signal, which is fed to a UW detector 741.
In UW detector 741, the electric power value of the crosscorrelation signal and a threshold value Sth2′ are compared, and if the electric power value of the crosscorrelation signal exceeds the threshold Sth2′, UW detector 741 outputs a FA-mode UW detection signal.
The quasi-synchronous detection signal outputted from matched filter 712 is retained in data buffer 713 until the FA-mode UW detection signal is outputted from UW detector 741.
Upon reception of the FA-mode UW detection signal from UW detector 741, data buffer 713 outputs the quasi-synchronous detection signal stored in data buffer 713, which has been received from matched filter 712, to a multiplier 750.
Multiplier 750 multiplies the output signal from data buffer 713 with the output from NCO 751, and outputs a data signal.
A clock regenerator (CR) 752 regenerates the clock from the output of multiplier 750 and feeds it to NCO 751. Upon reception of the output from multiplier 750, a symbol timing regenerator (STR) 753 outputs the symbol timing to sampling signal generator 702.
Hereafter, the operation of signal detection circuit 700 will be described.
In order to detect the position of the unique word UW accurately and to extend the range of measurement while maintaining the frequency offset measurement accuracy, this scheme, which is based on the above-described unique word delay detection circuit (DDD) 600 of FIG. 15, has an operation state called an initial acquisition mode (“IA mode”), in which DDD(N) 720 and DDD(N/2) 730 with different numbers of delay symbols are provided.
FIG. 17 shows a flowchart of a series of processes that are performed for the detection of the unique word UW in signal detection circuit 700.
The IA-mode unique word delay detection circuit used in the IA mode comprises unique word delay detection circuit (DDD(N)) 720 with the number of delay symbols N (where 0.5<N≦1) and unique word delay detection circuit (DDD(N/2)) 730 with the number of delay symbols N/2.
In the IA-mode unique word delay detection circuit, a first and a second crosscorrelation signal are generated by DDD(N) 720 and DDD(N/2) 730 on the basis of the first quasi-synchronous detection signal, which has been obtained by subjecting the orthogonal modulated signal having a known unique word UW inserted into the data signal to quasi-synchronous detection (step S701).
If the electric power value of the first crosscorrelation signal outputted from DDD(N) 720 exceeds the first threshold value Sth1′, UW detector 721 generates an IA-mode UW detection signal indicating the detection of the unique word UW from the supplied first quasi-synchronous detection signal. Meanwhile, in response to the first and second crosscorrelation signals from DDD(N) 720 and DDD(N/2) 730, phase combiner 723 generates IA-mode frequency offset information indicating a frequency offset F0 of the first quasi-synchronous detection signal (step S702).
In signal detection circuit 700, in order to prevent false UW detection, the FA-mode UW delay detection circuit operates in the fine-tuning acquisition mode following the detection (step S702) of the aforementioned unique word UW in the IA mode.
The FA-mode UW delay detection circuit comprises a UW delay detection circuit (DDD(N/4)) 740 with the number of delay symbols 4N for use in the FA mode.
The FA-mode UW delay detection circuit multiplies the outputs of the IA-mode unique word delay detection circuit, namely the first quasi-synchronous detection signal (output from data buffer 710) with the frequency correction signal (output from NCO 724), which responds to the IA-mode frequency offset information, thereby producing the second quasi-synchronous detection signal, in which the frequency offset is reduced to substantially zero. The second quasi-synchronous detection signal is fed to matched filter 712 in which noise or adjacent channel interference is reduced (step S703) and onto DDD(4N) 740, which outputs the FA-mode crosscorrelation signal (step S704).
In response to the crosscorrelation signal outputted from DDD(4N) 740, if the electric power value of the FA-mode crosscorrelation signal exceeds the second threshold Sth2′, the FA-mode UW delay detection circuit generates the FA-mode UW detection signal indicating the detection of the unique word UW from the second quasi-synchronous detection signal that corresponds to the first quasi-synchronous detection signal (step S705).
Upon the generation of the above FA-mode UW detection signal (step S705), signal detection circuit 700 ends the UW detection operation and enters a steady mode (“SS mode”), where the detection circuit operates as a demodulation circuit in which the second quasi-synchronous detection signal is subjected to synchronous detection and the data signal is demodulated (step S706).
In bi-directional communications, however, there are cases where the received signal is demodulated and a signal must be transmitted based on the information obtained from the received signal.
When the time between the reception of a signal and the start of transmission is defined, such as in this case, it is necessary to start the demodulation process as soon as possible.
Thus, in the case of the conventional OFDM demodulation circuit 400 as described above, if the preamble signal is detected erroneously, it is impossible to detect the error until the demodulation process is complete and an error detection is performed. Therefore, the demodulation process cannot be terminated, which may result in a failure to detect the original signal while the erroneous signal is being demodulated.
In the case of the conventional signal detection circuit 700, which was described subsequently, it is only after the received signal is subjected to delayed detection, its result is further subjected to delayed detection once again, and the result is outputted that the demodulation process is initiated. Thus, it takes a great deal of time before the demodulation process can be initiated after the reception of a signal.
Further, this signal detection circuit is not provided with a means to terminate the demodulation process in case an erroneous signal detection occurs.
In view of the aforementioned problems, it is the object of the invention to provide an OFDM demodulation circuit in which a demodulation process is initiated within a short period of time after the reception of a signal, and in which, in case the demodulation process is initiated erroneously, the demodulation process can be terminated as soon as possible. The invention also aims to provide an OFDM reception apparatus utilizing the OFDM demodulation circuit.